DMA buffer Concurrency

Let's say i have a DMA channel writing into a buffer at random intervals. What if i wanna write to the same buffer from the CPU, would there be a possible race condition problem? I suppose i cannot put a mutex on the DMA channel write. How would i do safely ?

You could maybe use IRQ so that the CPU can see when the DMA is done?

You could also think about if you need the CPU to write to the buffer at all. IIrc, DMA can also do buffer to buffer.

I actually have 8 dma channels writing to a buffer each time they're triggered by a PIO FIFO write. This means that the buffer always contains the last value from the PIOs But there could be cases where the PIO do not write to the fifo for a long time, and i dont want to take the last value from the buffer in those cases. So i want to write a zero to the buffer each time i read it in order to know if i already read it (if there is still a zero, there is no new value)

Wouldn't IRQ for each DMA channel fix the problem?